1. Field of the Invention
The present invention relates to a capacitor of a semiconductor device and a method for fabricating the same. More particularly, the present invention is directed to a capacitor that uses a material containing bismuth (Bi) such as (Bi,La)4Ti3O12 (BLT), SrBi2Ta2O9 (SBT) or SrxBiy(TaiNbj)2O9 (SBTN), as its dielectric substance, and to its method of fabrication.
2. Description of Related Art
Generally, research has been conducted to develop a device that provides a large capacity, which is required for a dynamic random access memory (DRAM) device, by using ferroelectrics for fabricating a capacitor of a semiconductor memory device.
A ferroelectric Random Access Memory (FeRAM) device employing a ferroelectric layer is a nonvolatile memory device. With the advantage of retaining stored information even when the electrical power is turned off and its operational speed just as fast as a DRAM, it stands in the spot light as the next-generation memory device.
The ferroelectrics used as dielectric substances for the FeRAM devices include (Bi,La)4Ti3O12 (BLT), SrBi2Ta2O9 (SBT), SrxBiy(TaiNbj)2O9 (SBTN), BaxSr(1xe2x88x92x)TiO3 (BST) and Pb(Zr,Ti)O3 (PZT), that have the Perovskite structure. The ferroelectric layers are applied to nonvolatile memory devices because their dielectric constants are as big as several hundred to several thousand at room temperature, and exist in a state of having two stable remnant polarizations (Pr).
A nonvolatile memory device employing a ferroelectric layer makes use of the hysteresis property, which inputs a signal by controlling the direction of polarization towards that of an electric field supplied thereto and, when the electric field is removed, stores a digital signal xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99 by the direction of the remaining remnant polarization (Pr).
Ferroelectrics such as BLT, SBT and SBTN have big dielectric constants, so they have the advantage that they can secure a sufficient capacitance in a small capacitor area when used as a cell capacitor of a memory device. For this reason, many studies are being conducted to develop a ferroelectric capacitor employing a BLT, SBT or SBTN thin layer as a cell capacitor in a memory device of several giga bits.
FIG. 1 is a cross-sectional view of a conventional ferroelectric capacitor using a material including Bi as its dielectric substance.
As illustrated in FIG. 1, the conventional method for fabricating a ferroelectric capacitor comprises the steps of: forming a first inter-layer insulation layer 12 on a semiconductor substrate 11 formed of transistors and bit lines (not shown); forming a contact mask that uses a photoresist on top of the first inter-layer insulation layer 12; and forming a contact hole that exposes a predetermined surface portion of the semiconductor substrate 11 by etching the first inter-layer insulation layer 12 with the contact mask.
Subsequently, polysilicon is formed on the first inter-layer insulation layer 12 including the contact hole, and a polysilicon plug 13 is formed in a predetermined part of the contact hole where it is recessed to a predetermined depth by performing an etch-back process.
Subsequently, titanium (Ti) is deposited on the entire surface and a rapid thermal process (RTP) is performed, and then Ti-silicide 14 is formed on the polysilicon plug 13 by the chemical reaction between the titanium and the silicon (Si) atom of the polysilicon plug 13. The Ti-silicide 14 forms an ohmic contact between the polysilicon plug 13 and the subsequent bottom electrode.
Thereafter, a TiN layer 15 is formed on the Ti-silicide 14. The TiN layer is polished chemically and mechanically (CMP) or etched back until the surface of the first inter-layer insulation layer 12 is exposed and made to remain in the contact hole only.
Here, the TiN layer 15 serves as a barrier metal that protects substances from being diffused from the bottom electrode into the polysilicon plug 13 or the semiconductor substrate 11.
After the formation of the TiN layer 15, an adhesive layer 16 is formed on the first inter-layer insulation layer 12 to improve the inter-layer adhesion, and a bottom electrode 17, a ferroelectric layer 18 containing bismuth (Bi) and top electrode 19 are formed in that order.
When forming the ferroelectric layer 18 containing bismuth (Bi) on the bottom electrode 17 formed of Pr, Ru, RuO2, Ir, IrO2, IrO or RuO, the ferroelectric layer 18 is deposited at a high temperature so as to be crystallized, or a subsequent thermal treatment process is conducted after the ferroelectric layer 18 containing bismuth (Bi) is deposited.
The reason for requiring the crystallization process is that when the ferroelectric layer 18 containing bismuth (Bi) has a polycrystalline structure, the ferroelectric layer 18 can manifest its properties as a ferroelectric material, such as remnant polarization and a large dielectric constant.
However, the crystallized ferroelectric layer has the shortcoming that its properties as a ferroelectric capacitor are degraded because its grain boundaries are used as conduction paths for the leakage of current, thus bringing about an increase in the leakage current and the dielectric loss.
Also, bismuth is the most volatile among the materials forming ferroelectric material. Therefore, when performing subsequent high temperature thermal treatments, the Bi on the surface of the ferroelectric layers may volatilize, thereby not manifesting the inherent properties of ferroelectric layers.
As described above, various methods have attempted to solve the problems of ferroelectric layers containing Bi, such as current leakage and deterioration of ferroelectric properties, for instance, by using diverse materials as electrodes or adding impurities, only to obtain so far unsatisfactory.
It is, therefore, an object of the invention to provide a capacitor of a semiconductor device and a fabrication method therefore that reduces current leakage and dielectric loss.
In accordance with an embodiment of the invention, there is provided a capacitor of a semiconductor device, comprising: a first electrode formed on a substrate; a ferroelectric layer containing bismuth formed on the first electrode; a second electrode formed on the ferroelectric layer containing bismuth; and an amorphous bismuth oxide layer positioned at, at least one of the locations between the first electrode and the ferroelectric layer and between the ferroelectric layer and the second electrode.
In accordance with an embodiment of the invention, there is provided a method for fabricating a semiconductor device, comprising the steps of: forming a first electrode on a substrate; forming a ferroelectric layer containing bismuth on the first electrode; performing a rapid thermal process (RTP) to crystallize the ferroelectric layer; forming a second electrode on the ferroelectric layer containing bismuth; forming an amorphous bismuth oxide layer positioned at, at least one of the places between the first electrode and the ferroelectric layer and between the ferroelectric layer and the second electrode.
Further scope of applicability of the invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.